Motorola MVME147 Installation And Use Manual page 128

Functional Description
DMAC Initiation Mode
5
DMAC Operation States
Idle State
Data Transfer State
5-12
The DMAC has two initiation modes: direct and command
chaining (scatter-gather).
In the direct mode, the data address pointer and the byte count are
loaded into the chip.
In the command chaining mode, a table of data addresses and byte
counts is placed in local RAM and the address of the table is loaded
into the chip. The chip walks through the addresses and byte counts
from the local RAM to move each block of data as indicated by the
table. Scatter-gather operations are supported by command
chaining.
The PCC can DMA to/from local DRAM and VMEbus memory
only. Any other access results in a local bus time-out.
The DMAC is always in one of three operational states: idle state,
table walk state, or data transfer state. The DMA sequences through
the three depending upon the contents of the DMA control register
which is initialized by the MPU.
The DMAC starts out from reset in the idle state. It stays in the idle
state until the DMAC is enabled (DMAEN set to 1). It returns to the
idle state when the DMAC has completed the requested operations
(normally or with error). It does not leave the idle state again until
all error status bits are cleared and DMAEN is again set to 1.
When DMAEN is set, the DMAC goes directly to the data transfer
state unless the Table Walk (TW) bit is set. If TW is set, the DMAC
table walks before entering the data transfer state.
In either event, when the data transfer state is entered, the DMAC
moves data between local DRAM and the WD33C93 (SCSI bus
interface controller). The DMAC reads/writes data in local DRAM