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Programming
Table Address Register
4
Data Address Register
4-4
This 32-bit read/write register points to a table of physical
addresses and byte counts that are used during DMA transfers
when table mode is selected. The table address must be longword
aligned because bits 0 and 1 are always zero. If the table address has
bit 0 or 1 set, they are truncated and no error is generated. These bits
are not affected by reset. Refer to Chapter 5 for details on Table
Address.
FFFE1000
This 32-bit read/write register points to the physical address where
data is to be transferred. Data can only be transferred to/from
onboard DRAM or VMEbus memory. These bits are not affected by
reset.
FFFE1004
Table Address
Data Address
0
0
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