Motorola MVME147 Installation And Use Manual page 68

Programming
DMA Status Register
ADDRESS
FFFE1023
4
Bits 0-3
Bits 4-7
4-18
BIT 7 BIT 6 BIT 5
Inc 4 Inc 3 Inc 2
R R R
The PCC has a 32-bit register which is used to hold data that is
transferred between the SCSI bus and the local bus. Bits 0-3
indicate the status of each byte of the holding register (byte
position in longword: UU = upper upper; UM = upper middle;
LM = lower middle; LL = lower lower). When a bit is low, the
corresponding byte is empty. When a bit is high, the
corresponding byte is full. These bits are cleared when the DMA
controller is disabled. These bits are cleared by reset.
The DMA address and byte counters may be incremented by 1,
2, 3, or 4. When the DMA counters are incremented, the
increment value is saved in these bits. Only one of the 4 bits is
set. These bits are cleared when the DMA controller is disabled.
These bits are cleared by reset.
BIT 4 BIT 3 BIT 2
Inc 1 UU UM
R R R
BIT 1 BIT 0
LM LL
R R