Motorola MVME147 Installation And Use Manual page 77

Slave Base Address Register
ADDRESS BIT 7
FFFE102B LANA25
R/W
Note
Bits 0-4
Table 4-2. DRAM Address as Viewed from the VMEbus
RBA4 RBA3 RBA2 RBA1 RBA0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
0 0 1
0 1 0
0 1 0
0 1 0
0 1 0
0 1 1
0 1 1
0 1 1
0 1 1
Programming the Peripheral Channel Controller
BIT 6 BIT 5
LANA24 WAITRMC
R/W R/W
All bits are cleared by reset.
These bits set the slave RAM base address, or the address of
onboard RAM as viewed from the VMEbus.
Beginning
Address
0 0 $00000000
0 1 1 x DRAMsize (2 x DRAMsize)-1
1 0 2 x DRAMsize (3 x DRAMsize)-1
1 1 3 x DRAMsize (4 x DRAMsize)-1
0 0 4 x DRAMsize (5 x DRAMsize)-1
0 1 5 x DRAMsize (6 x DRAMsize)-1
1 0 6 x DRAMsize (7 x DRAMsize)-1
1 1 7 x DRAMsize (8 x DRAMsize)-1
0 0 8 x DRAMsize (9 x DRAMsize)-1
0 1 9 x DRAMsize (10 x DRAMsize)-1
1 0 10 x DRAMsize (11 x DRAMsize)-1
1 1 11 x DRAMsize (12 x DRAMsize)-1
0 0 12 x DRAMsize (13 x DRAMsize)-1
0 1 13 x DRAMsize (14 x DRAMsize)-1
1 0 14 x DRAMsize (15 x DRAMsize)-1
1 1 15 x DRAMsize (16 x DRAMsize)-1
BIT 4 BIT 3 BIT 2
RBA4 RBA3 RBA2
R/W R/W R/W
Ending
Address
(1 x DRAMsize)-1
BIT 1 BIT 0
RBA1 RBA0
R/W R/W
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
4-27
4