Motorola MVME147 Installation And Use Manual page 145

Local RAM Parity Error
When parity checking is enabled, the current bus master receives a
bus error (or no LANRDY*, if LANCE) if it is accessing the local
DRAM and a parity error occurs. If the MC68030 is the local bus
master when the parity error occurs, the Parity Error (PE) status bit
is set in the PCC status register. Note that this bit is only useful if
mode 3 parity checking is set. If mode 2 parity checking is set, the
MC68030 is not able to read status after the occurrence of the parity
error.
Bus Error Processing
Because different conditions can cause bus error exceptions, the
software must be able to distinguish the source. To aid in this, the
MVME147 provides status bits in the VMEchip and PCC chip.
Generally, the bus error handler can interrogate the status bits and
proceed with the result. However, two conditions can corrupt the
status bits:
A VMEbus slave reports an access error (such as parity error).
Whenever a VMEbus BERR* occurs, the VMEbus BERR*
status bit is set in the VMEchip.
An interrupt can happen during the execution of the bus
error handler (before an instruction can write to the status
register to raise the interrupt mask). If the interrupt service
routine causes a second bus error, the status that indicates the
source of the first bus error may be lost. The software must be
written to deal with this. The PCC can be programmed to
generate a Level 7 interrupt when a bus error occurs. This
may help force the MC68030 to a known place when a bus
error occurs.
The PCC can take a VMEbus bound BERR* (which updates
the status bits) between the MC68030 receiving and handling
of a bus error, or vice-versa.
Sources of Bus Error (BERR*)
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