Motorola MVME147 Installation And Use Manual page 46

Operating Instructions
Interrupt Acknowledge Map
3
VMEbus Memory Map
VMEbus Accesses to MVME147 Onboard DRAM
3-8
The MC68030 distinguishes interrupt acknowledge cycles from
other CPU space cycles by placing the binary value %1111 on A19-
A16. It also specifies the level that is being acknowledged using
A03-A01. The interrupt handler selects which device within that
level is being acknowledged. Refer to Interrupt Handler in Chapter 5.
The following paragraphs describe the mapping of MVME147
resources as viewed by VMEbus masters.
The MVME147 onboard DRAM, VMEchip global registers, and
VMEbus interrupter respond to accesses by VMEbus masters. No
other devices on the MVME147 respond to such accesses.
When a VMEbus master accesses the MVME147 onboard DRAM, it
must do so using the address modifier selected by a control register
in the VMEchip and the base address selected by a control register
in the PCC. Refer to Table 3-6.