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Document History Page
Document Title: CYW43903 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14826
Revision
ECN
**
–
*A
–
*B
–
*C
5445059
*D
5593296
*E
5909757
*F
5986964
*G
6026132
Document Number: 002-14826 Rev. *G
PRELIMINARY
Orig. of
Submission
Change
Date
43903-DS100-R
–
10/15/2015
Initial Release
–
11/03/2015
Updated:
Table 21: "Absolute Maximum Ratings", Table 24: "Recommended Operating
Conditions and DC Characteristics", Table 30: "WLAN 2.4 GHz Receiver
Performance Specifications", Table 31: "WLAN 2.4 GHz Transmitter Performance
Specifications"
43903-DS102-R
–
03/12/2016
Updated:
General edits
Added Cypress Part Numbering Scheme and Mapping Table.
UTSV
11/28/2016
Updated to Cypress template.
Removed 43909 Documentation.
TREB
01/24/2017
Updated Cypress Logo and Copyright.
Updated 512 KB to 1 MB in the following pages:
UTSV
10/12/2017
Features on page
Applications CPU and Memory Subsystem on page
Updated "Broadcom Serial Control (BSC)" to "Cypress Serial Control (BSC)"
SHJL
12/11/2017
throughout the document.
Added VBAT in
Updated the footnotes in
Deleted 3.3 Frequency Selection and Real-Time Clock.
Added " Note : JTAG_SEL is exposed on a dedicated physical pin. TAP_SEL uses
the GPIO_8 physical pin." below
Added " Note: The high-speed, 4-wire UART interface is identified as UART0 in this
document and in reference schematics. The two low-speed,
2-wire UART interfaces are identified as UART1 and UART2 in this document and
in the reference schematics" in the
Added footnote in
Added section
Added
Updated footnote of
SHJL
1/11/2018
to ~26.67MHz for reliable operation at high operating temperatures. The throughput
of the SPI Flash block is therefore restricted to ~13 MBps for Quad mode and ~3
MBps for single mode".
Added " The clock for the SPI Flash block needs to be constrained to ~26.67MHz for
reliable operation at high operating temperatures.
The throughput of the SPI Flash block is therefore restricted to ~13 MBps for Quad
mode and ~3 MBps for single mode." to 22.3.Errata.
Description of Change
43903-DS101-R
1,
Figure 1 on page
Figure 1 on page
Table 4 on page
Table 11 on page 36
SPI on page
19.
Errata on page 63
5.5 SPI Flash
2,
Figure 2 on page
5,
Features on page
16.
2.
14.
Table
6.
UART on page
18.
and
Table 30 on page
54.
as "Note that the clock needs to be constrained
CYW43903
6,
Page 64 of 65
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