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9. Pinout and Signal Descriptions
9.1 Ball Map
P
N
M
RF_SW_
12
VDDIO
CTRL_8
RF_SW_
11
SRSTN
VSSC
CTRL_9
RF_SW_
10
JTAG_SEL
NC_N10
CTRL_5
RF_SW_
RF_SW_
RF_SW_
9
CTRL_2
CTRL_3
CTRL_0
8
OTP_VDD3P3
AVDD1P2
LPO_XTAL_IN
WRF_XTAL_
WRF_XTAL_
7
AVSS
XON
GND1P2
WRF_XTAL_
WRF_XTAL_
WRF_XTAL_
6
XOP
VDD1P35
VDD1P2
WRF_PMU_
WRF_SYNTH_
WRF_SYNTH_
5
VDD1P35
VDD1P2
GND
WRF_RX5G_
WRF_AFE_
WRF_GENERAL
4
GND
VDD1P35
_GND
WRF_GENERAL
WRF_AFE_
3
RF_GND_P3
2_GND
GND
WRF_PA_
WRF_TXMIX_
2
RF_GND_P2
GND3P3
VDD
WRF_PA_
WRF_
1
VDD3P3
PAOUT_2G
P
N
M
Document Number: 002-14826 Rev. *G
PRELIMINARY
Figure 11. 151-Ball WLBGA Map—Top View with Balls Facing Down
L
K
J
RF_SW_
PWR_GND
NC_J12
CTRL_7
RF_SW_
VSSC
NC_J11
CTRL_1
RF_SW_
VDDC
NC_J10
CTRL_6
RF_SW_
VDDIO_RF
VSSC
CTRL_4
VSSC
VDDIO_RF
VDDIO
VDDC
VDDIO
WRF_SYNTH_
VDDC
VSSC
VDD3P3
WRF_VCO_
VDDC
VSSC
GND
WRF_EXT_
VSSC
TSSIA
WRF_GPAIO_
HIB_REG_
HIB_LPO_
HIB_WAKE_B
OUT
ON_IN
SELMODE
WRF_RX2G_
VSSC
HIB_XTALOUT
GND
WRF_RFIN_
HIB_REG_ON_O
VSSC
VDDC
2G
L
K
J
H
G
F
NC_H12
GPIO_3
GPIO_6
VOUT_3P3
VDDC
NC_G11
GPIO_5
VSSC
GPIO_2
GPIO_4
NC_H9
VSSC
VSSC
VSSC
VDDC
VSSC
VDDC
VSSC
VDDC
VDDC
VSSC
VSSC
HIB_XTALIN
VSSC
VDDC
HIB_VDDO
VDDC
UT
H
G
F
E
D
C
LDO_
LDO_
VDDBAT5V
VDD1P5
VDDBAT5V
VOUT_
VDDIO
VOUT_LNLDO
VOUT_CLDO
HSICLDO
VOUT_
VDDIO
VSSC
PMU_AVSS
CLDO_SENSE
VDDIO
GPIO_8
VSSC
I2C0_SDATA
GPIO_13
VSSC
I2C0_CLK
UART0_TXD
VSSC
UART0_RXD
UART0_RTS
SPI0_CS
GPIO_12
SPI0_SISO
GPIO_7
SPI0_MISO
SPI0_CLK
VDDC
SFL_IO3
SFL_IO2
VSSC
VDDC
VSSC
SFL_IO1
GPIO_9
VSSC
GPIO_16
GPIO_0
GPIO_1
GPIO_10
GPIO_11
E
D
C
CYW43903
B
A
SR_
SR_PVSS
12
SR_VLX
11
WL_REG_ON
10
VDDC
9
VDDIO
8
UART0_CTS
7
SFL_CS
6
SFL_CLK
5
SFL_IO0
4
GPIO_14
3
VSSC
GPIO_15
2
1
B
A
Page 27 of 65
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