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15.5 BBPLL LDO
Table 29. BBPLL LDO Specifications
Parameter
Input supply voltage, V
in
Output voltage, V
o
Dropout voltage
Output voltage DC
accuracy
Output current
Quiescent current
Line regulation
Load regulation
Leakage current
PSRR
Start-up time of PMU
LDO turn-on time
Inrush current
External output capacitor,
C
o
External input capacitor
Document Number: 002-14826 Rev. *G
PRELIMINARY
Conditions and Comments
Min. V
= V
+ 0.15V = 1.35V (for V
in
o
The dropout voltage requirement must be met under maximum
load.
Programmable in 25 mV steps. Default = 1.2V.
At max. load
Includes line/load regulation.
Peak load = 80 mA, average = 35 mA
No load
55 mA load
V
from (V
+ 0.15V) to 1.5V; 200 mA load
in
o
load from 1mA to 200 mA; V
Powered down. Junction temperature is 85°C.
Bypass mode
@1 kHz, V
≥ V
+ 0.15V, Co = 4.7 μF
in
o
VIO up and steady. Time from REG_ON rising edge to CLDO
reaching 99% of V
.
o
The LDO turn-on time when the rest of the chip is up.
Vin=Vo+0.15V to 1.5V, Co=0.47uF, no load
Ceramic, X5R, size 0201, max. 6.3V, 20% tolerance
Only use an external input capacitor at the LDO_VDD1P5 pin if it
is not supplied from the CBUCK output.
= 1.2V).
o
≥ (V
+ 0.15V)
in
o
CYW43903
Min.
Typ.
Max.
1.3
1.35
1.5
V
1.1
1.2
1.275
V
–
–
150
mV
–4
–
+4
%
0.1
–
55
mA
–
10
12
μA
–
550
570
μA
–
–
5
mV/V
–
0.025
0.045
mV/mA
–
5
20
μA
–
0.2
1.5
μA
20
–
–
dB
–
530
700
us
–
140
180
us
–
60
70
mA
0.27
0.47
–
μF
–
1
–
μF
Page 53 of 65
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