Spi - Infineon Cypress WICED CYW43903 Manual

5.7 SPI

CYW43903 contains one SPI block. This block support a fixed SPI mode (CPOL = 0, CPHA = 0) and 8-bit data read/write.
CPOL = 0: Clock idles at 0, and each cycle consists of a pulse of 1. The leading edge is a rising edge, and the trailing edge is a
■
falling edge.
CPHA = 0: The "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the
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data on (or shortly after) the leading edge of the clock cycle.
The SPI hardware block supports a hold time of 25ns and a maximum clock frequency of 40MHz. If a SPI slave does not support the
above mode or requires a hold time greater than 25ns, a bit banging software SPI driver should be used. Cypress's WICED SDK
provides and example of such a driver.
Note that the maximum SPI frequency support by a software SPI driver is much lower than 40 MHz.
SPI0 mentioned in Table 8
Document Number: 002-14826 Rev. *G
PRELIMINARY
is multiplexed with GPIOs and can therefore support a bit banging based software SPI driver.
CYW43903
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