Power Management; Pmu Sequencing - Infineon Cypress WICED CYW43903 Manual

2.3 Power Management

The CYW43903 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43903 includes an advanced Power Management Unit (PMU) sequencer. The PMU
sequencer provides significant power savings by putting the CYW43903 into various power management states appropriate to the
environment and activities that are being performed. The power management unit enables and disables internal regulators, switches,
and other blocks based on a computation of the required resources and a table that describes the relationship between resources
and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters
(running at a 32.768 kHz LPO clock) in the PMU sequencer are used to turn on and turn off individual regulators and power switches.
Clock speeds are dynamically changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever
possible.
Table 2 provides descriptions for the CYW43903 power modes.
Table 2. CYW43903 Power Modes
Mode
Active All WLAN blocks in the CYW43903 are powered up and fully functional with active carrier sensing and frame
transmission and receiving.
All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds
are dynamically adjusted by the PMU sequencer.
Doze The radio, analog domains, and most of the linear regulators are powered down.
The rest of the CYW43903 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or
TCXO) are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for
the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition
to Active mode. In Doze mode, the primary power consumed is due to leakage current.
Deep-sleep Most of the chip, including both analog and digital domains and most of the regulators, is powered off.
Logic states in the digital core are saved and preserved in a retention memory in the Always-On domain before
the digital core is powered off. Upon a wake-up event triggered by the PMU timers or an external interrupt, logic
states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
Power-down The CYW43903 is effectively powered off by shutting down all internal regulators.
The chip is brought out of this mode by external logic re-enabling the internal regulators.

2.4 PMU Sequencing

The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a compu-
tation of required resources and a table that describes the relationship between resources and the time required to enable and disable
them.
Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
enabled
■
disabled
■
transition_on
■
transition_off
■
The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loaded
with the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled and
decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to
enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0
indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence
refer to either the immediate transition or the timer load-decrement sequence.
Document Number: 002-14826 Rev. *G
PRELIMINARY
Description
CYW43903
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