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13.5 Power Supply Segments
The digital I/O's are placed in physical segments. The supply voltage for each segment can be independently selected.
Table 17
shows the power supply segments and the I/O pins associated with each segment.
Table 17. Power Supply Segments
Power Supply Segment
VDDIO
VDDIO_RF
13.6 GPIO, UART, and JTAG Interfaces DC Characteristics
Table 18. GPIO, UART, and JTAG Interfaces
Parameter
Logic input high voltage
Logic input low voltage
Logic output high voltage
Logic output low voltage
Document Number: 002-14826 Rev. *G
PRELIMINARY
GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, GPIO_8, GPIO_9,
GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, GPIO_15, GPIO_16, I2C0_CLK,
I2C0_SDATA, I2C1_CLK, I2C1_SDATA, JTAG_SEL, SFL_CLK, SFL_CS, SFL_IO0, SFL_IO1,
SFL_IO2, SFL_IO3, SPI0_CLK, SPI0_CS, SPI0_MISO, SPI0_SISO, SPI1_CLK, SPI1_CS,
SPI1_MISO, SPI1_SISO, SRSTN, UART0_CTS, UART0_RTS, UART0_RXD, UART0_TXD
RF_SW_CTRL_0, RF_SW_CTRL_1, RF_SW_CTRL_2, RF_SW_CTRL_3, RF_SW_CTRL_4,
RF_SW_CTRL_5, RF_SW_CTRL_6, RF_SW_CTRL_7, RF_SW_CTRL_8, RF_SW_CTRL_9
Symbol
Minimum
V
2.0
IH
V
–0.5
IL
V
2.4
OH
V
–
OL
Pins
Maximum
Units
VDDIO + 0.5
V
0.8
V
–
V
0.4
V
CYW43903
Conditions
–
–
–
–
Page 43 of 65
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