Gpio Signals And Strapping Options; Overview; Weak Pull-Down And Pull-Up Resistances; Strapping Options - Infineon Cypress WICED CYW43903 Manual

10. GPIO Signals and Strapping Options

10.1 Overview

This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various
operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each
pin assumes the GPIO or alternative function specified in
(PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to
ground, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.

10.2 Weak Pull-Down and Pull-Up Resistances

At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of VDDO) are 37.99 kΩ,
44.57 kΩ, and 51.56 kΩ, respectively. At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-up resistances (for a
pin voltage of 0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively.

10.3 Strapping Options

Table 9 provides the strapping options.
Table 9. Strapping Options
Pin Name
GPIO_1 GSPI_MODE
GPIO_7 WCPU_BOOT_MODE
GPIO_11 ACPU_BOOT_MODE
GPIO_13 SDIO_MODE
GPIO_15 VTRIM_EN
RF_SW_CTRL_5 DAP_CLK_SEL
RF_SW_CTRL_7 RSRC_INIT_MODE
Document Number: 002-14826 Rev. *G
PRELIMINARY
Table
Default Internal
Strap #
D1 PD
E5 PD
B1 PD
E8 PD
A2 PD
M10 PD
L12 PD
10. Each strapping option pin has an internal pull-up (PU) or pull-down
Pull During
Strap
Enable gSPI interface
Boot from SoC SROM or SoC SRAM
Boot from tightly coupled memory (TCM) ROM or TCM
RAM
Select either SDIO host mode or SDIO device mode
Enable PMU voltage trimming
Select XTAL clock or the test clock (tck) for the debug
access port (DAP)
PMU resource initialization mode selection
CYW43903
Description
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