Applications Subsystem External Interfaces; Gpio; Cypress Serial Control; Jtag And Arm Serial Wire Debug - Infineon Cypress WICED CYW43903 Manual

5. Applications Subsystem External Interfaces

5.1 GPIO

There are 17 general-purpose I/O (GPIO) pins available on the CYW43903. The GPIOs can be used to connect to various external
devices.
Upon power-up and reset, these pins are tristated. Subsequently, they can be programmed to be either input or output pins via the
GPIO control register. In addition, the GPIO pins can be assigned to various other functions.
Apart from other functions, GPIOs are used to set bootstrap options and use the JTAG interface for debugging during software
development.

5.2 Cypress Serial Control

The CYW43903 has two Cypress Serial Control (CSC
etc. The I/O pads can be configured as pull-ups or pull-ups can be installed on the reference design to support a multimaster on an
open drain bus.

5.3 JTAG and ARM Serial Wire Debug

The CYW43903 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-
ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
The CYW43903 also supports ARM Serial Wire Debug (SWD) for connecting a JTAG debugger directly to both ARM Cortex-R4s. For
SWD, the combination of a clock and a bidirectional signal (on a single pin) provides normal JTAG debug and test functionality. The
reduced pin-count SWD interface is a high-performance alternative to the JTAG interface.
Table 6 shows the JTAG_SEL and TAP_SEL states for test and debug function selection. Test and debug function selection is
independent of the debugging interface (JTAG or SWD) being used.
Table 6. JTAG_SEL and TAP_SEL States for Test and Debug Function Selection
JTAG_SEL State TAP_SEL State
0 0
0 1
1 0
1 1
Note: JTAG_SEL is exposed on a dedicated physical pin. TAP_SEL uses the GPIO_8 physical pin.
2. Cypress Serial Control is an I
Document Number: 002-14826 Rev. *G
PRELIMINARY
2
) master interfaces for external communication with codecs, DACs, NVRAM,
JTAG not used.
JTAG not used.
Access the LV tap directly for ATE and bring-up.
Access either of the ARM Cortex-R4's directly via either the 5-pin JTAG port or the 2-pin
SWD configuration.
2
C compatible interface.
Test and Debug Function
CYW43903
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