Write-Register Timing - Infineon Cypress WICED CYW43903 Manual

17.1.2 Write-Register Timing

Figure 14 shows the SPI flash extended and quad write-register timing.
Note: Regarding Figure 14:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended for each protocol: to 23 for extended and five for quad.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Extended
0
C
DQ0 Command
MSB
Quad
0
C
DQ[3:0] Command
MSB
Document Number: 002-14826 Rev. *G
PRELIMINARY
Figure 14. SPI Flash Write-Register Timing
7 8 9
LSB
D D
IN IN
MSB
1 2 3
LSB
LSB
D D D
IN IN
MSB
10 11 12
D D D
IN IN IN
IN
CYW43903
13 14 15
LSB
D D D
IN IN IN
D
IN
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