Digilent Genesys ZU Reference Manual page 7

Zynq UltraScale+ MPSoC Architecture
Zynq UltraScale+ MPSoC is the Xilinx second‐generation Zynq platform, combining a powerful processing
system (PS) and user‐programmable logic (PL) into the same device. The Zynq UltraScale+ Processing
System core acts as a logic connection between the PS and the Programmable Logic (PL) while assisting
you to integrate customized and integrated IP cores with the processing system using the Vivado IP
integrator. As you may see in the picture below, the processing system features the Arm flagship Cortex
‐A53 64‐bit quad‐core running up to 1.5GHz and Cortex‐R5 dual‐core real‐time processor along with
other interfaces such as: DDR Memory Controller, High‐Connectivity, General Connectivity, System
Functions etc. The Zynq UltraScale+ MPSoC Processing System wrapper instantiates the processing
system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The
wrapper includes unaltered connectivity with the ones presented above.
Figure II: Zynq UltraScale+ EG
The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user‐
created hardware accelerators and other functions in the PL logic that are accessible to the processors.
The interfaces between the processing system and programmable logic mainly consist of three main
groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups. Besides
those, there are up to 78 Multiplexed I/O (MIO) ports available from the processing system. The 78 MIO
signals are divided into three banks, and each bank includes 26 device pins. Each bank (500, 501, and
502) has its own power pins for the hardware interface.