Digilent Genesys ZU Reference Manual page 15

VCC1V1
VCC0V9_MGTAVCC*
VCC0V9_VCU*
VCC0V85_PSMGTRAVCC V CC2V7_LDOIN 0.825V / 0.85V /0.875V
VCC0V85_INT
VTT0V6
VREF0V6
1.3. Power Sequencing
The board is powered up by sliding the SW5 switch to the ON position. The voltage supplies start‐up
sequence is defined by implementing a power good daisy chain that selectively enables groups of
voltages that should start together. All supplies use a soft start mechanism to reduce the surge currents
during turn on. The start‐up sequence is suggested in Figure 1.2.1 and can be described in the following
steps:
When the ramping VCC12V0 exceeds the turn‐ON threshold of IC78, the VCC5V0_STABLE rail starts up.
This triggers the VCC3V3_STABLE supply and powers the IC81 internal logic. The VCC3V3_STABLE rail
powers the platform MCU. Its valid state is marked by the green Aux power ON LED (LD19).
When the protection circuit detects a valid 12V input, it asserts the INPUT_PGD signal that triggers the
VCC5V0 startup. This voltage powers the internal logic of IC83 and IC84.
If VCC5V0 reaches its power‐good threshold, the PGOOD0=En1 signal is asserted. This enables the
VCC0V85_INT, VCC0V9_MGTAVCC*, VCC2V7_LDOIN and VCC0V9_VCU* voltages. The power‐good
signals of all these supplies are joined in a wired AND configuration and activate PGOOD1 when all rails
have reached their nominal voltages.
When all voltages from the first starting group have crossed their power‐good thresholds, the
PGOOD1=En2 signal is asserted. This enables the VCC1V8_AUX and VCC0V85_PSMGTRAVCC voltages of
the second group.
VCC1V8_AUX 1V/ 1.1V/ 1.155V
VCC12V0 0.873V / 0.9V / 0.927V
VCC12V0 0.873V / 0.9V / 0.927V
VCC12V0 0.825V / 0.85V / 0.875V
0.6V (0.49xVCC1V2_PSDDR‐
VCC1V2_PSDDR 0.02V...
...0.51xVCC1V2_PSDDR+0.02V)
0.6V (0.49xVCC1V2_PSDDR...
VCC1V2_PSDDR
...0.51xVCC1V2_PSDDR)
0.49A Ethernet, HDMI
FPGA Internals (5EV
0.55
variant only)
FPGA Internals (5EV
2A
variant only)
0.3A FPGA Internals
11A FPGA Internals
1A DDR4 VTT
DDR4 reference
0.01A
voltage