Digilent Genesys ZU Reference Manual page 16

A similar trigger mechanism applies to the third (PGOOD2=En3) and the fourth (PGOOD3=En4) voltage
groups as illustrated in Figure 1.2.1. The fourth group also includes the dedicated DDR4 power supply
with all its output voltages.
If all voltages from the fourth group have succesfully reached their designed values, their power‐good
(PG_ALL) lights up the green Main Power ON LED (LD20). At this point the board is fully functional.
Note: the VADJ rail is controlled separately by the platform MCU that must first set VADJ depending on
the peripherals using those voltage. VADJ is in the fourth start‐up group but it is conditioned by a valid
EN_VADJ_CTRL signal generated by the platform MCU.
Sliding the SW5 switch to the OFF position disables the power supplies by pulling INPUT_PGD to ground.
The capacitor C405 connected to the EN terminal of the LM5060 monitoring IC delays the VCC12V0 turn
off with approximately 200ms until all power supplies have been safely powered off.
2. MPSoC Boot Process
Figure 2.1: Genesys ZU Boot Diagram
2.1. JTAG Boot Mode
JTAG is the most important component of the debug features for software and PL development. The
JTAG architecture has three Test Access Port (TAP) controllers:
PS TAP (main PS controller with IDCODE)