Digilent NetFPGA-SUME Reference Manual

NetFPGA-SUME™ Reference Manual
Revised April 11, 2016
This manual applies to the NetFPGA-SUME rev. C
Overview
Powered by Xilinx's Virtex-7 XC7V690T
FPGA, the NetFPGA-SUME is an ideal
platform for high-performance and
high-density networking design.
32 GTH serial transceivers have been
used to provide access to 8 lanes of
end-point PCI-E (Gen3 x8), 4 SFP+
(10Gbps) ports, 2 SATA-III ports
(6Gbps), and 18 data-rate-adjustable
GTH ports through a HPC-FMC
connector and a QTH connector.
Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB
DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.
Features include:
FPGA

Xilinx Virtex-7 XC7V690T FFG1761-3
Memory

Two 4GB DDR3 SODIMMs (MT8KTF51264Hz-
1G9E1)

64 bit wide buses clocked at
850 MHz (1700 mbps)

Three 72Mbit QDRII+ SRAMs
(CY7C25652KV18-500BZXC)

36 bit wide buses clocked at
500 MHz (1000 mbps)
Storage

Two SATA III ports (6 gbps via GTH
transceivers)

Micro-SD Card Slot

Two 512Mbit Micron StrataFlash parallel flash
modules (PC28F512G18A)

For bitfile storage only
Communication Interfaces

PCI-E Gen3 x8 supporting 8Gbps/lane

Four SFP+ interfaces supporting 10Gbps

Four globally unique MAC addresses

USB-UART

I2C Pmod port
DOC#: 502-301
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The NetFPGA-SUME board.
Expansion Connectors

QTH Connector (8 GTH transceivers)

One HPC FMC Connector (10 GTH transceivers
and 68 User I/Os)

One 12-pin Pmod port (8 User I/Os)
Programming

Micro USB Connector for JTAG programming and
debugging (shared with USB-UART interface)

Xilinx CPLD XC2C512 for FPGA configuration from
parallel flash
Power Management

Two Linear Technology Power System Managers
(LTC2974)

Provide current measuring on all major
power rails
Other Features

User LEDs and Push Buttons

PROG Push Button for manual FPGA Reset

FPGA Configuration LEDs

I2C Mux (PCA9548A) for controlling all onboard
I2C buses
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