Digilent Genesys ZU Reference Manual page 20

controller's restrictions. These are detailed in the Zynq UltraScale+ Device Technical Reference Manual
(UG1085), but common modules of 1R/2R, x8/x16, 64b/72b are supported.
The serial presence detect (SPD) interface is wired to MIO8 (DDR_SCL) and MIO9 (DDR_SDA), accessible
through the I2C1 controller.
For better routing some byte swaps were performed detailed in Table 3.1.1. No nibble or bit swaps were
needed.
Table 3.1.1: DDR4 interface byte swaps.
System 7
Slot 0
ECC byte (lane 8) is equivalent to any of the data bytes from the perspective of the DRAM components.
The controller and SODIMM connector have dedicated ECC pins (CBx), which are not used on non‐ECC
systems. Therefore the ECC lane (CBx) cannot be swapped with other lanes. However, byte and bit
swaps in data lanes are transparent to the ECC feature since any swap performed upon write is reversed
back upon read.
The Write CRC is a new feature of DDR4 and is complementary and unrelated to the ECC feature. Write
CRC protects data in transit, ECC protects data in storage. CRC is calculated both by the controller and
the DRAM to avoid data corruption in the the write data burst. It can detect single bit, double bit, odd
count and one multi‐bit UI vertical column errors. Upon error detection, DRAM will assert the ALERT_n
line. The controller should retry the write upon error.
It should be enabled in systems that expect a high amount of signal integrity issues and where high
reliability is desired. It trades data rate for reliability. CRC support is optional in SODIMM modules. Even
if the module supports it, implementation is not easy. For CRC to work the controller must know what
pin swaps were performed on the memory interface. In case of SODIMM modules, there are some
restricted pin swaps possible and must be documented in the SPD EEPROM. The controller is expected
to read these, combine it with pin swaps on the system board and assign the bits to CRC inputs
accordingly. According to AR# 68788 this can be achieved through the DDRC.DQMAP registers, not well
documented.
4. Storage
4.1. Quad‐SPI Flash
6 5
1 2
4 3 2
3 4 5
1 0 8
6 7 8