Digilent Genesys ZU Reference Manual page 29

8. Expansion Ports
8.1. Mini PCIe / mSATA
J13 socket implements a versatile expansion option for adding SSD, WLAN, Bluetooth or WWAN
modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full‐Mini) and
H1/H2 (Half‐Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the
relocatable stand‐offs included with the board. Electrically, the SATA lane and the PCIe x1 lane share the
same PS‐GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA
or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the
embedded USB 2.0 port wired to the on‐board USB hub and the MPSoC USB1 controller up the chain.
8.2. Low‐Pin Count FMC Connector
The Genesys ZU includes an FPGA Mezzanine Card (FMC) Standard‐conforming carrier card connector
that enables connecting mezzanine modules compliant with the same standard. Genesys ZU‐based
designs can now be easily extended with custom or off‐the‐shelf high‐performance modules.
The actual connector used is a 160‐pin Samtec ASP‐134603‐01, the low‐pin count, 10mm stacking height
variant of the standard. All user defined signals are bonded to the PL‐side of the MPSoC to HP banks 64
and 65. On the 5EV variant the multi‐gigabit transceiver lane is also wired to the PL‐side GTH
transceiver, sharing the lane with the SFP+ slot.* The 34 differential pairs are powered by the Genesys
ZU VADJ rail adjustable in the 1.2 V ‐ 1.8 V range.
FMC mezzanine cards are NOT hot‐swappable. Connecting or disconnecting a card from the Genesys ZU
while the board is powered on may cause damage to the mezzanine card and/or the board, and is to be
avoided.
The UltraScale+ HP banks support the highest data rates available in the non‐GT I/O architecture over
the FMC connector.
The pin‐out of the FMC connector can be found in the XDC constraints file available on
reference.digilentinc.com. The schematic also shows the mapping between FMC connector pins and
FPGA pins. Keep in mind that pin designators for the connector are not the same as pin designators for
the FPGA specified in the XDC constraints file. For example, the connector pin with designator H28 and
named LA24_P is wired via net FMC_LA24_P to the FPGA pin with designator AF7 and named
IO_L11P_T1U_N8_GC_64. In the constraints file FMC_LA24_P will need to be location constrained to
AF7.
For above‐gigabit speed rates on the 5EV variant, the gigabit transceiver lane is wired to a multiplexer.
The SFP+ slot and the FMC share a single GTH lane through the multiplexer. Therefore, only one of them