Digilent Genesys ZU Reference Manual page 14

VCC12V0
VCC5V0_STABLE
VCC5V0
VCC3V3_STABLE
VCC3V3
VADJ
VCC2V5
VCC1V8_AUX
VCC1V8_MGT
VCC1V5_PCI
VREF1V25
VCC1V2_MGTAVTT
VCC1V2_PSDDR
12V power
12V+‐5%
input
VCC12V0 5V+‐5%
VCC12V0 5V+‐5%
VCC5V0_STABLE 3 .16V / 3.3V / 3.465V
VCC12V0 3.154V / 3.3V / 3.4V
Selectable ‐ 1.2V / 1.5V / 1.8V +‐
VCC12V0
5%
VCC12V0 2.375V / 2.5V / 2.625V
VCC12V0 1.746V / 1.8V / 1.854V
VCC2V7_LDOIN 1.746V / 1.8V / 1.854V
VCC12V0 1.5V=‐5%
VCC3V3 1.25V+‐5%
VCC12V0 1.164V / 1.2V/ 1.236V
VCC12V0 1.14V / 1.2V/ 1.26V
FMC, power input for
8.5A
other rails
IC81+IC80 ,
0.306A
VCC3V3_STABLE
SYZYGY, RGB LED,
4A Audio, USB‐s, HDMI Rx
AUX
Platform MCU, Supply
I2C pull‐ups, FMC, SFP,
0.224A
HDMI Clock, PCIe
REFCLK
DDR4 VDDSPD (I2C
interface), PCAMs,
LEDs, SFP, HDMI, FMC,
FPGA Internals,
7.64A SYZYGY, PMODs, PCIe,
SD Card, WI‐FI, USB
3.0, USB 2.0 Hub, USB
Config, Display Port,
Flash
2.4A FMC, SYZYGY, FPGA
DDR4 VPP, MGT
2.1A
Oscillators, Ethernet
FPGA Internals,
Ethernet, DisplayPort,
1.59A
Audio, USB 3.0, USB
2.0, USB Prog, SD Card
0.09A FPGA Internals
0.5A PCIe port
0.01A XADC reference
0.77A FPGA Internals
6.87A FPGA Internals, DDR4