Digilent Genesys ZU Reference Manual page 31

Each SYZYGY Standard interface contains 14 single‐ended I/O pins (2 of which I2C), 8 differential I/O
pairs (which can alternatively be used as 16 additional single‐ended I/O pins), and two dedicated
differential clocks ‐ one for input and one for output. The Zmod port is wired to PL‐side MPSoC banks
powered by the VADJ rail, sharing them with FMC signals. Therefore if both an FMC mezzanine card and
a Zmod are connected to the Genesys ZU, a common voltage supported by both needs to be chosen for
VADJ. The differential pairs were prioritized and wired to HP banks, allowing the maximum data rates
supported by the SelectI/O architecture. However, the single‐ended pins are wired to an HD bank,
limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC
Switching Characteristics (ds925). Template constraints for the Zmod port can be found in the Genesys
ZU's Master XDC file, available through Digilent's digilent‐xdc repository on Github.
For more information on the SYZYGY standard, see syzygyfpga.io.
8.3.1. SYZYGY Pod Compatibility
The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required
to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 8.3.1.1.
Table 8.3.1.1: SYZYGY Compatibility
Parameter
Port Type
Total 5V Supply Current
Total 3.3V Supply Current
VIO Supply Voltage Range
Total VIO Supply Current
Port Groups
I/O Count
Length Matching
8.3.2
Is there any information on this not encapsulated by the syzygy spec?
Port A (STD)
Standard
Single‐Width
1 A
3.5 A (shared with FMC)
1.2V to 1.8V
2.1 A (shared with FMC)
Group 1: A
28 total (8 DP)
10 mm inter‐pair, 1mm intra‐pair