IBM Power System S822LC Installing The System And Ordered Parts page 77

Figure 54. PCIe3 FPGA Compression Accelerator Adapter
Specifications
Item Description
Adapter FRU number
000NK006 (Designed to comply with RoHS requirement)
I/O bus architecture
PCIe3 x8
Slot requirement
One PCIe x8 or x16 slot (Low-profile)
Voltage
3.3 V, 12 V
Form factor
Full-height (FC EJ12) and short, low-profile (FC EJ13)
Maximum number
For details about the maximum number of adapters that are supported, see PCIe adapter
placement rules and slot priorities (http://www.ibm.com/support/knowledgecenter/POWER8/
p8eab/p8eab_mtm_pciplacement.htm) and select the system you are working on.
Attributes provided
High throughput compression that saves storage and I/O bandwidth with little or no overhead
CPU offload and PCIe interface with negligible software load frees up CPU cores for higher value
computation or licensed software
Lower power consumption by offloading the CPU intensive compression to an FPGA
Widely used zlib and gzip standard format for data interchange
Up to 1.8 GB/s compression and decompression throughput
3-25x speed up achievable
Compression ratio near software zlib and gzip
Multiple uses including genomics, data center, cloud, and backup solutions
Installing and configuring system features
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