ZiLOG eZ80F92 User Manual page 84

eZ80F92 Development Kit
User Manual
74
input
General Array Logic Equations
nEX_FL_DIS, //disables Flash on the expansion
//module, when Low
nEM_EN, //enables Development Platform LED
//and Port A emulation circuit
nDIS_FL, //disables Module Flash when Low
nL_RD, //enables local data bus to be read by CPU
nmemen1,
nmemen2,
nmemen3,
nmemen4
);
nFL_DIS /* synthesis loc="P4"*/,
nCS0 /* synthesis loc="P5"*/,
nCS2 /* synthesis loc="P3"*/, //was 23
A7 /* synthesis loc="P6"*/,
A6 /* synthesis loc="P7"*/,
A5 /* synthesis loc="P9"*/,
A4 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A2 /* synthesis loc="P12"*/,
A1 /* synthesis loc="P13"*/,
A0 /* synthesis loc="P16"*/,
nEX_FL_DIS /* synthesis loc="P2"*/;
//input[7:0]A;upper part of Address Bus of F92
//A23=A7,A22=A6,A21=A5,A20=A4,A19=A3
//A18=A2,A17=A1,A16=A0
PRELIMINARY UM013904-0203