ZiLOG eZ80F92 User Manual page 29

Pin # Symbol
37 SDA
38 GND
39 FlashWE
40 GND
41 CS3
42 DIS_IrDA
43 RESET
44 WAIT
45 V
DD
46 GND
47 HALT_SLP
48 NMI
49 V
DD
50 Reserved
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F92 Module Schematics
through 64.
2. The Power and Ground nets are connected directly to the eZ80F92 device.
Almost all of the connectors' signals are received directly from the CPU.
Three input signals, in particular, offer options to the application devel-
oper by disabling certain functions of the eZ80F92 Flash Module.
UM013904-0203
®
Table 3. eZ80
I/O Connector Identification—JP2* (Continued)
Signal Direction
Bidirectional
Output
Input
Output
Bidirectional
Output
Input
Output
PRELIMINARY
eZ80F92 Development Kit
Development Platform
Active Level
Low
Low
Low
Low
Pull-Up 10KΩ; Low
Low
Low
User Manual
2
eZ80F92 Signal
Yes
No
Yes
No
Yes
Yes
Yes
Yes
on pages 62
Operational Description
19