ZiLOG eZ80F92 User Manual page 32

eZ80F92 Development Kit
User Manual
22
Signal Pin #
PC[7:0] 39,41,43,
45,47,49,
51,53
ID_[2:0] 6,8,10
CON_DIS 12
Reserved 16,18
PD[7:0] 22,24,26,
28,30,32,
34,36
PB[7:0] 40,42,44,
46,48,50,
52,54
Note: *All of the signals are driven directly by the CPU.
Operational Description
Table 4. GPIO Connector J6* (Continued)
Function
Port C, Bit [7:0]
®
eZ80
Development
Platform ID
Console Disable
Port D, Bit[7:0]
Port B, Bit[7:0]
PRELIMINARY
Direction Notes
Bidirectional
Output
Input If a shunt is installed between
pins 12 and 14, the Console
function on the eZ80
Development Platform is
disabled.
Bidirectional
Bidirectional
®
UM013904-0203