Figure 23. Schematic Diagram, #2 Of 9-100-Pin Qfp Ez80F92 - ZiLOG eZ80F92 User Manual

eZ80=IIC-bus-master
IICSDA
IICSDA
IICSCL
IICSCL
CLK_OUT
CLK_OUT
PB[0..7]
PB[0..7]
PC[0..7]
PC[0..7]
PD[0..7]
PD[0..7]
-RESET
-RESET
JTAG[1..4]
JTAG[1..4]
TDO
TDO
-RD
-RD
-WR
-WR
-IOREQ
-IOREQ
-MREQ
-MREQ
-INSTRD
-INSTRD
-WAIT
-WAIT
-HALT_SLP
-HALT_SLP
-BUSREQ
-BUSREQ
-BUSACK
-BUSACK
-NMI
-NMI
A[0..23]
A[0..23]
-CS[0..3]
-CS[0..3]
D[0..7]
D[0..7]
RTC_VDD
RTC_VDD
UM013904-0203
PB[0..7]
IICSDA
IICSCL
CLK_OUT
A0
1
A0
A1
2
A1
A2
3
A2
A3
4
A3
A4
5
A4
A5
6
A5
7
VDD
8
VSS
A6
9
A6
A7
10
A7
A8
11
A8
A9
12
A9
A10
13
A10
A11
14
A11
A12
15
A12
A13
16
A13
A14
17
A14
18
VDD
19
VSS
A15
20
A15
A16
21
A16
A17
22
A17
A18
23
A18
A19
24
A19
A20
25
A20
A[0..23]
-CS[0..3]
V3.3 V3.3 V3.3
D[0..7]
PLACE CAPS CLOSE
C21 C22 C23
1nF 1nF 1nF
TO PINS
97,7,33,43
Figure 23. Schematic Diagram, #2 of 9—100-Pin QFP eZ80F92 Device
PC[0..7]
PD7/RI0
PD6/DCD0
PD5/DSR0
PD4/DTR0
PD3/CTS0
PD2/RTS0/IR_SD
PD1/RxD0/IR_RXD
U8
PD0/TxD0/IR_TXD
VDD
TDO
TDI (ZDA)
eZ80F92
TRIGOUT
TCK (ZCL)
TMS
VSS
RTC_VDD
TQFP100
RTC_XOUT
RTC_XIN
VSS
VDD
HALT_SLP
BUSACK
BUSREQ
NMI
RESET
PRELIMINARY
eZ80F92 Development Kit
XIN
R31 0
XOUT
C16
20pF
PD[0..7]
PD7
75
PD6
74
PD5
73
PD4
72
PD3
71
PD2
70
PD1 JTAG[1..4]
69
PD0
68
67
TDO (= JTAG0)
66
TDI = JTAG1
65
TRIGOUT = JTAG2
64
TCK = JTAG3
63
TMS = JTAG4
62
61
RTC_VDD
60
RTC_XOUT
59
RTC_XIN RTC_VDD
58
57
56
C18
-HALT_SLP
55
100nF
-BUSACK
54
-BUSREQ
53
R29
-NMI
52
-RESET
51
10k
R32
RTC_XIN
220 Y3
32.768kHz
XTAL3
RTC_XOUT
C24
18pF
User Manual
65
20 MHz
Y2
HC49SM
100K
R27
C17
20pF
R37
0
V3.3
R28
100
D1
TMM BAT 41
MINIMELF_AK
GoldCap
C19
0,1F
GOLDCAP_SD
V3.3
C20
18pF
VDD
VSS
GND
Schematic Diagrams