ZiLOG eZ80F92 User Manual page 60

eZ80F92 Development Kit
User Manual
50
//Init_IRDA
// Ensure to first set PD2 as a port bit, an output and set it Low.
PD_ALT1 &= 0xFC;
PD_ALT2 |= 0x03;
UART_LCTL0= 0x80;
BRG_DLRL0=0x2F;
BRG_DLRH0=0x00;
UART_LCTL0=0x00;
UART_FCTL0=0xC7;
UART_LCTL0=0x03;
IR_CTL = 0x03;
//IRDA_Xmit
IR_CTL = 0x01;
Putchar(0xb0);
Operational Description
enables received data to pass into the UART0 Receive FIFO data buffer.
Bit 2 is a test function that provides a loopback sequence from the TxD
pin to the RxD input.
Bit 1, the Receive Enable bit, is used to block data from filling up the
Receive FIFO when the eZ80F92 Flash Module is transmitting data.
Because IrDA data passes through the air as a light source, transmitted
data can also be received. This Receive Enable bit prevents this data from
being received. After the eZ80F92 Flash Module completes transmitting,
this bit is changed to allow for incoming messages.
The code that follows provides an example of how this function is
enabled on the eZ80F92 Flash Module.
// PD0 = uart0tx, PD1 = uart0_rx
// Enable alternate function
// Select dlab to access baud rate generator
// Baud rate Masterclock/(16*baudrate)
// High byte of baud rate
// Disable dlab
// Clear tx fifo, enable fifo
// 8bit, N, 1 stop
// enable IRDA Encode/decode and Receive
// enable bit.
//Disable receive
//Output a byte to the uart0 port.
PRELIMINARY UM013904-0203