Spi Timing Characteristics - Atmel AVR AT90CAN32 Manual

2. Required only for f
3. C = capacitance of one bus line in pF.
b
4. f = CPU clock frequency
CK
5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the
Two-wire Serial Bus need only obey the general f
6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f
greater than 6 MHz for the low time requirement to be strictly met at f
7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f
requirement will not be strictly met for f
bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a
proper t acceptance margin.
LOW
Figure 26-3. Two-wire Serial Bus Timing
SCL
t
SU;STA
SDA
26.6

SPI Timing Characteristics

AT90CAN32/64/128
370
> 100 kHz.
SCL
> 308 kHz when f
SCL
t
t HIGH
of
t
LOW
t
HD;STA
See Figure 26-4 and Figure 26-5
Table 26-4. SPI Timing Parameters
Description
1 SCK period
2 SCK high/low
3 Rise/Fall time
4 Setup
5 Hold
6 Out to SCK
7 SCK to out
8 SCK to out high
9 SS low to out
10 SCK period
11 SCK high/low
12 Rise/Fall time
requirement.
SCL
SCL
= 8 MHz. Still, AT90CAN32/64/128 devices connected to the
CK
t
LOW
t
HD;DAT t
SU;DAT
for details.
Mode Min.
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave 4 • t
(1)
Slave 2 • t
Slave
- 2/f
SCL CK
= 100 kHz.
- 2/f
SCL CK
t
r
t
SU;STO
Typ.
See Table 16-4
50% duty cycle
3.6
10
10
0.5 • t
sck
10
10
15
ck
ck
), thus f must be
CK
), thus the low time
t
BUF
Max.
ns
1.6 µs
7679H–CAN–08/08