Parallel Programming Characteristics - Atmel AVR AT90CAN32 Manual

System Clock (CLK )
CPU
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
DA7:0 (XMBK = 0)
RD

26.10 Parallel Programming Characteristics

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Figure 26-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1)
T1 T2
1
4 7
2 3a 13
Address XX
6
3b
Address
5 10
8
Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the
RAM (internal or external).
Figure 26-10. Parallel Programming Timing, Including some General Timing Requirements
XTAL1
Data & Contol
(DATA, XA0/1, BS1, BS2)
PAGEL
WR
RDY/BSY
T3 T4
Address
15
Data
16
9
Data
12
t
XHXL
t t
DVXH
t
BVPH
t
PHPL
(1)
T5 T6
11
t
XLWL
XLDX
t t
PLBX
BVWL
t
WLWH
t
PLWL
WLRL
T7
14
t
WLBX
t
WLRH
7679H–CAN–08/08