Asynchronous Data Reception - Atmel AVR AT90CAN32 Manual

17.8.6 Disabling the Receiver
17.8.7 Flushing the Receive Buffer
17.9

Asynchronous Data Reception

17.9.1 Asynchronous Clock Recovery
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will
no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag
is cleared.
The following code example shows how to flush the receive buffer.
Assembly Code Example
USART0_Flush:
lds r16, UCSR0A
sbrs r16, RXC0
ret
lds r16, UDR0
rjmp USART0_Flush
(1)
C Code Example
void USART0_Flush (void)
{
unsigned char dummy;
while (UCSR0A & (1<<RXC0) ) dummy = UDR0;
}
Note: 1. The example code assumes that the part specific header file is included.
The USARTn includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
(1)
Figure 17-5
7679H–CAN–08/08