Clock Correction Sequence - Xilinx LogiCORE IP Spartan-6 Getting Started Manual

Clock Correction Sequence

The Clock Correction Sequence screen (page 10) of the Wizard
clock correction sequence. See
X-Ref Target - Figure 3-14
Table 3-24: Clock Correction Sequence
Option
Set each symbol to match the pattern the protocol requires. The PCI EXPRESS sequence length is 8
Byte (Symbol) bits. 00011100 is used for the first symbol of sequence 1. The remaining symbols are disabled
because the Sequence length is set to 1.
This option is available when 8B/10B decoding is selected. When checked, the symbol is an 8B/10B
K Character
K character.
Some protocols with 8B/10B decoding use symbols with deliberately inverted disparity. This
Inverted Disparity
option should be checked when such symbols are expected in the sequence.
Multiple-byte sequences can have wild card symbols by checking this option. Unused bytes in the
Don't Care
sequence automatically have this option set.
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
Table 3-24 for details.
Figure 3-14: Clock Correction Sequence - Page 10
Description
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Generating the Core
(Figure 3-14) defines the
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