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Theory of Operation
Output Latches
Eight-bit transparent latch UlOOl serves as an 8-bit output port from MPU U700. When pin 11 of UlOOl is high,
the latch inputs drive the outputs. When the latch-enable input goes low, U820 latches its outputs. The
outputs are constantly on because the OE(L) input is wired low. IC U910 is an 8-bit, edge-clocked latch with
constantly on outputs. When low, the EN(L) input allows the data inputs to be latched in whenever th,e CP
input goes high.
UlOOS
The C and D sections of hex-inverter UlOOS are wired as a two-input NOR gate and used to address an 8-bit
output port UlOOl. UlOOSA and UlOOSB serve as output drivers for the probe data lines (from the 11AS2 to any
attached probes). Because UlOOS is an open-collector part, the probes can also pull down on the probe data lines
to send messages to the l 1AS2. Diodes VR7S7 and VR7S9 protect the probe data lines from static voltages.
Reset Circuit
Reset IC U660 disables the CPU while the amplifier is powering up or down. The reset circuit keeps the RESET
input of microprocessor U700 low unless the output of +SD supply falls below +4.SS V. At power-up, the pin 2
input of U660 (Rin) holds RESET high. When the +SD supply reaches +4.SS V ±50 mV, U660 will produce a low
on RESET after 13 ms. Capacitor C660 sets this delay time. When RESET goes low, the CPU can begin executing
stored instructions.
(
At power-down, when the +SD supply decays to +4.SS V, U660 sets RESET high.
Analog Control/Signal Amplifiers <3>
This section describes the electrical operation and relationship of circuits in the analog control circuitry and
signal amplifiers. See Schematic <3> in Section 6.
Sample/Hold Assemblies
The S/H boards contain only surface-mounted components which are coated with insulating material to
minimize leakage current. A defective S/H assembly is not repairable and should be replaced.
One-of-eight analog multiplexer UlOO periodically updates the voltages on ClOO through CllS. Inputs Al, Bl,
and Cl of UlOO are the avenue through which UlOO receives the address of the selected holding capacitor,
while the S/H IN input receives the voltage to be applied to that capacitor. Amplifiers U102 and Ul03,
which have very high input impedance and unity gain, are used to buffer the voltages on holding capacitors
ClOO through CllS while UlOO is updating those voltages. The holding capacitors can be charged only when
the UlOO's ENl input is low.
Analog multiplexer UlOl provides a readback path for self-testing analog voltage outputs Vl through V8,
which are normally in the range of ±1.14 V. The READBACKO, READBACKl, and READBACK2 lines contain
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11A52 Extended Service Manual
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Table of Contents
Troubleshooting
