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NOT RECOMMENDED FOR
NEW
DESIGNS
DS1220Y
READ MODE
The DS 1220Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active
(low).
The unique address specified by the 11 address inputs
(AO-A IO) defines which of the 2Q48 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tAcc (Access Time) after the last address input signal is
stable,
providing
-
-
-
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either
tco
for CE or
toE for OE rather than address
access.
WRITE MODE
The DS 1220Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
-
-
cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be
initiated.
The OE control signal should be kept inactive (high) during
write cycles to avoid bus
contention. However,
if the output drivers are enabled (CE and OE active)
then WE will disable the outputs in toow from its falling edge.
DATA RETENTION MODE
The DS1220Y provides fu11-functional capability for Vee greater than 4.5 vo1ts and write protects at 4.25
nominal. Data is maintained in the absence of V cc without any additional support circuitry. The
DS1220Y constantly monitors Vee. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become "don't care," and all outputs become high-impedance. As V cc falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During
power-up,
when V cc rises above approximately 3.0 vo1ts, the power switching circuit
connects external V cc to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after V cc exceeds 4.5
volts.
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Troubleshooting
