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Theory of Operation
Signal Amplifiers
Signal Amplifiers U310 and U410 are shown on schematic 3. The main amplifiers do all the voltage
amplification required. Input signals come from the individual attenuators through shielded cables into J210
and J521. The nominal gain of the Signal Amplifiers is 1.09 (at 50 m
VI
div); the gain of the attenuator is 0.915
(in lX attenuation). The combined gain from the plug-in BNC connector to the plug-in edge connector is 1.00.
Each main amplifier is a hybrid that contains:
a.
A differential, high-speed input with the +Vin terminated in 50
Q
and overvoltage protected to ±25 V
(pin 4). The -Vin is not terminated and has no overvoltage protection (pin 8).
b.
Three separate differential outputs (pins 19-20, 22-23, and 25-26) that can be individually turned on,
turned off, or inverted using the OUTPUT INVERT and OUTPUT ON control lines
(pins 11-12, 15-16, 17-18).
c.
Two four-pole bandwidth-limit filters: one at 20 MHz and another at 100 MHz. See Table 2-6.
TABLE2-6
Bandwidth Limit vs. BPO and BP1 Bits
Bandwidth
BPl
BPO
20MHz
0
0
lOOMHz
0
1
Maximum
1
x
d.
Six gain settings of 1 m V, 2 m V, 5 m V, 10 m V, 20 m V, and 50 m V per division. See Table 2-7.
TABLE2-7
Gain Set by GPO, GP1, and GP2 Bits
Gain
Setting
GP2
GPl
GPO
lmV
0
0
0
2mV
0
0
1
5mV
0
1
0
lOmV
0
1
1
20mV
1
0
x
50mV
1
1
x
The signals GPO, GPl, GP2 plus BPO and BPl connect to pins 1, 36, 35, 34, and 33 of both U310 and U410. The
GP and BP lines are latched using the strobe lines GSl(L) and GS2(L).
e.
On-chip, TTL-compatible latch circuitry to store the bandwidth and gain settings. The latches are loaded
when the strobe input is low. See the GSl(L) and GS2(L) on schematic 3.
f.
Three separate high-frequency adjust inputs per channel, one for each signal amplifier.
2-16
11A52 Extended Service Manual
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Table of Contents
Troubleshooting
