Kernel; Analog Control Voltage System - Tektronix 11A52 Service Manual

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Theory of Operation
Normally pin 7 of U350 is near zero volts, which saturates Q449. When saturated, Q449 furnishes current to
U850 through CR449 and L755. Diode CR449 drops 0.7 V to lower the power dissipated in the attenuator relays.
Inductor L755 and C850 bypass the relay power to reduce digital noise at the attenuators.
Kernel <2>
This section describes the electrical operation and relationship of circuits in the control circuitry. See
Schematic <2> in Section 6.
Analog Control Voltage System
The Analog Control Voltage System (ACVS) generates DC voltage levels used to set input offsets, balance, and
amplifier gains. The ACVS also nulls the input current and adjusts the high frequency response of each
channel. The main ACVS components are the Housekeeper IC (U600), digital-to-analog converter (DAC) U630,
and the Sample/Hold modules (AlAl, A1A2).
Circuitry in U600 drives both the DAC and the Sample/Hold modules. Every 30 µs U630 is driven to one of 16
voltage levels stored in U600's memory. Each AlAl output is updated every 300 µs while each A1A2 output is
updated every 1200 µs, or 1/ 4 as often. The DAC is a two-byte, latched-data unit, which means that the high
and low data bytes are loaded separately into the DAC. U600 produces LCLK and UCLK, which together
control the latching of the individual high and low data bytes. The upper byte is latched in first by UCLK
pulsing low. Then the signal LCLK pulses low, which transfers in the lower byte and tells the DAC that the
12-bit value is valid.
While the DAC is being driven, the Sample/Hold modules are given the address of a selected output using
signals ARAO, ARAl, and ARA2; then strobed with the signals MAJSTB(L) and MINSTB(L). The DAC is
internally set to produce precisely +5.0 V maximum and -5.0 V minimum. Resistors R527 and R525 divide the
DAC output to ±1.136 V to create the VDAC signal, which drives the Sample/Hold modules directly.
11A52 Extended Service Manual 2-7