Mpv - Tektronix 11A52 Service Manual

Theory of Operation
enough to prevent bleeding the AC coupling precharge signal voltage when the input coupling is changed from
Off to AC.
MPV
The CPU (U700) is an 8052 single-chip, 8-bit microcontroller. It contains an on-chip oscillator and clock
circuitry, 32 I/0 lines, 64 k address space for external data memory, 64 k address space for external program
memory, three 16-bit timer
I
counters, a six-source interrupt structure, full-duplex serial port, and a Boolean
processor. Port bit descriptions
(I
= Input, 0 = Output, Bi =Bi-directional) and usage.
Bit# Desc
PO.O
Bi
PO.I Bi
P0.2 Bi
P0.3 Bi
P0.4 Bi
P0.5 Bi
P0.6 Bi
P0.7 Bi
Pl.O
I
Pl.1
I
Pl.2
0
Pl.3 Bi
Pl.4
Bi
Pl.5
Bi
Pl.6 I
Pl.7
0
P2.0
0
P2.1
0
P2.2 0
P2.3 0
P2.4 0
P2.5 0
P2.6 0
P2.7
0
P3.0 0
P3.l 0
P3.2 I
INT I
P3.4
0
P3.5 0
WR(L)
0
RD(L)
0
2-10
TABLE
2-2
Port Bits
Usage
Output for the adrs latch & bi-directional data bus
Output for the adrs latch & bi-directional data bus
Output for the adrs latch & bi-directional data bus
Output for the adrs latch & bi-directional data bus
Output for the adrs latch & bi-directional data bus
Output for the adrs latch & bi-directional data bus
Output for the adrs latch
&
bi-directional data bus
Output for the adrs latch & bi-directional data bus
Attenuator checkback data (serially encoded)
A-D converter data (serially encoded)
Relay control
Signature Analyzer Clock
Signature Analyzer Start
Signature Analyzer Stop
AID I/ 0 Clock
Relay disable
Address bit 8 of the RAM
Address bit 9 of the RAM
Address bit 10 of the RAM
(not used)
Address bit used to enable the output latch (UlOOl)
Address bit used to enable RAM U801 and U600
Address bit used to enable the input latch (U910)
(not used)
Attenuator shift data (serially encoded)
Attenuator shift clock
(not used)
(P3.3) Interrupt from U600
A-D converter enable (U750)
Auxiliary trieeer on
(P3.6) Write (L)
(P3.7) Read(L)
·.
11A52 Extended Service Manual