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Theory of Operation
(
Random Access Memory
The Random Access Memory (RAM) is contained in the DS1220 battery backed up static RAM (U801). The
DS1220 is a 16,384 bit, fully static, nonvolatile memory module organized as 2048 words by eight bits. The
nonvolatile memory module has a self-contained lithium energy source and control circuitry that constantly
monitors +SD ( +S V digital supply) for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled
data.
An
unlimited number of write cycles can be executed and no additional support circuitry is required for
microprocessor interface. The pins labeled AO-AlO are the address lines, and the pins labeled DO-D7 are the
data lines.
Read Mode
The static RAM executes a read cycle when WR(L) is high and CS(L) is low. The unique address specified by
the 11 address inputs (AO-AlO) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data-output drivers within the access time after the last address input signal is stable.
Write Mode
The static RAM is in the Write mode when WR(L) and CS(L) are both low after the address inputs are stable.
The later occurring falling edge of CS(L) or WR(L) will determine the start of the write cycle, which is
terminated by the earlier rising edge of CS(L) or WR(L). All address inputs must be kept valid throughout the
write cycle.
Data Retention Mode
The nonvolatile RAM module provides full functional capability as long as +SD is greater than 4.S V, and
write-protects at 4.2S V nominal. Data are maintained in the absence of +SD with no additional support
circuitry. RAM U801 constantly monitors +SD. Should the supply voltage decay, the RAM will automatically
write-protect itself; all RAM inputs become "don't care," and all outputs are high impedance. As +SD falls
below approximately 3.0 V, the power-switching circuit connects the lithium energy source to the RAM. During
power-up, when +SD rises above approximately 3.0 volts, the power switching circuit connects external +SD to
the RAM, and disconnects the lithium energy source. Normal RAM operation can resume after +SD
exceeds 4.5 V.
Calibration Buffer Amplifier
Calibration Buffer Amplifier U841 provides unity-gain voltage following of the VCAL signal (B36 at edge
connector). To
reduc~
gain errors, the voltage is sensed inside each attenuator; U840 selectively switches the
sensed voltage between channels 1 and 2. The internal sense line is available at pin 3 of each attenuator. IC
U841B,
Q831
11
and Q830 provide power amplification of the VCAL signal while U841A senses the CALSENSE
feedback signal. Diodes CR830 and CR831 eliminate latch-up that could occur because Q830 and Q831 are
powered by ±S V. Q830 and Q831 are off during normal oscilloscope operation. During calibration K960 selects
the calibration buffer amplifier, which requires Q830 and Q831 to produce up to ±4.0 V into 2S
.Q
(two SO
.Q
attenuators driven in parallel). L96S, C96S, and C842 filter out low-level digital noise in the
calibration signal. C836, C841, C93S, R832 and R93S stabilize the amplifiers. R843 and R1041 (see schematic 1)
connect the CALSENSE line to the attenuator sense points. The values of R843 and R1041 were chosen to be high
11A52 Extended Service Manual
2-9
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Troubleshooting
