Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 5

MachXO2 Programming and Configuration Usage Guide
Configuration
The rising edge of the INITN pin causes the FPGA to enter the configuration state. The FPGA is able to accept the
configuration bitstream created by the Diamond development tools.
The MachXO2 begins fetching configuration data from non-volatile memory. The memory used to configure the
MachXO2 is either the internal Flash, or an external SPI Flash. The MachXO2 does not leave the Configuration
state if there are no memories with valid configuration data. It is necessary to program the non-volatile memory
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internal or attached to the FPGA, or to program it using the JTAG port. Only JTAG, SSPI and mode are allowed
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to be used as programming mode when the device is in a blank/erased state.
During the time the FPGA receives its configuration data the INITN control pin takes on its final function. INITN is
used to indicate an error exists in the configuration data. When INITN is high, configuration proceeds without issue.
If INITN is asserted low, an error has occurred and the FPGA will not operate.
Wake-up
Wake-up is the transition from configuration mode to user mode. The MachXO2's fixed four-phase wake-up
sequence starts when the device has correctly received all of its configuration data. When all configuration data is
received, the FPGA asserts an internal DONE status bit. The assertion of the internal DONE causes a Wake Up
state machine to run that sequences four controls. The four control strobes are:
• Global Output Enable (GOE)
• Global Set/Reset (GSR)
• Global Write Disable (GWDISn)
• External DONE
The first phase of the Wake-Up process is for the MachXO2 to release the Global Output Enable. When it is
asserted, permits the FPGA's I/O to exit a high-impedance state and take on their programmed output function.
The FPGA inputs are always active. The input signals are prevented from performing any action on the FPGA flip-
flops by the assertion of the Global Set/Reset (GSR).
The second phase of the Wake-Up process releases the Global Set/Reset and the Global Write Disable controls.
The Global Set/Reset is an internal strobe that, when asserted, causes all I/O flip-flops, Look Up Table (LUT) flip-
flops, distributed RAM output flip-flops, and Embedded Block RAM output flip-flops that have the GSR enabled
attribute to be set/cleared per their hardware description language definition.
The Global Write Disable is a control that overrides the write enable strobe for all RAM logic inside the FPGA. The
inputs on the FPGA are always active, as mentioned in the Global Output Enable section. Keeping GWDIS
asserted prevents accidental corruption of the instantiated RAM resources inside the FPGA.
The last phase of the Wake-Up process is to assert the external DONE pin. The external DONE is a bi-directional,
open-drain I/O only when it is enabled. An external agent that holds the external DONE pin low prevents the wake-
up process of the MachXO2 from proceeding. Only after the external DONE, if enabled, is active high does the final
wake-up phase complete. Wake-Up completes uninterrupted when the external DONE pin is not enabled.
Once the final wake-up phase is complete, the FPGA enters user mode.
The wake-up process is illustrated in Figure 18.
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