Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 15

of Diamond do not enable the stall feature when SDM_PORT enables DONE I/O). A common reason for keeping
DONE driven low is to allow multiple FPGAs to be completely configured. As each FPGA reaches the DONE state,
it is ready to begin operation. The last FPGA to configure can cause all FPGAs to start in unison.
The DONE pin drives low in tandem with the INITN pin when the FPGA enters Initialization mode. As described
earlier, this condition happens when power is applied, PROGRAMN is asserted, or an IEEE 1532 Refresh com-
mand is received via an active configuration port.
Sampling the DONE pin is a way for an external device to tell if the FPGA has finished configuration. However,
when using IEEE 1532 JTAG to configure SRAM the DONE pin is driven by a boundary scan cell, so the state of
the DONE pin has no meaning during IEEE 1532 JTAG configuration (once configuration is complete, DONE takes
on the behavior defined by the SDM_PORT setting in the Feature Row). The DONE pin is also pulled high when
the FPGA is in the Feature Row HW Default Mode state. This behavior can make a part appear to be successfully
configured to other logic monitoring the DONE pin.
Master and Slave SPI Configuration Port Pins
Table 9. Master SPI Configuration Port Pins
Pin Name Function
MCLK/CCLK MCLK
CSSPIN CSSPIN
SI/SISPI SISPI
SO/SPISO SPISO
SN SN/IO
Table 10. Slave SPI Configuration Port Pins
Pin Name Function
MCLK/CCLK CCLK
SI/SISPI SI
SO/SPISO SO
SN SN
MCLK/CCLK: The MCLK/CCLK, when active, are clocks used to sequentially load the configuration data for the
FPGA. The pin functions as:
The MCLK/CCLK pin's default state for a MachXO2 in the Feature Row HW Default Mode state is to act as the con-
figuration clock (i.e., CCLK). This allows an external Slave SPI master controller to program the MachXO2. The
maximum CCLK frequency and the data setup/hold parameters can be found in the AC timing section of DS1035,
MachXO2 Family Data
use the port to reprogram the MachXO2 after it enters user mode.
The MCLK/CCLK pin functions as a Master Clock (MCLK) when the MachXO2 is configured in Dual Boot or Exter-
nal Boot modes. A 1K pull-up resistor is recommended when using these modes. The MCLK becomes an output
MachXO2 Programming and Configuration Usage Guide
Direction
Output with weak pullup
Output
Output
Input
Input
Direction
Input with weak pullup
Input
Output
Input with weak pullup
Sheet. The Feature Row must be configured to ENABLE the Slave SPI Port if you want to
Master clock used to time data transmission/reception from the
MachXO2 Configuration Logic to a slave SPI PROM. A 1K pull-up
resistor is recommended on MCLK for External and Dual Boot
configuration modes.
Chip select used to enable an external SPI PROM containing con-
figuration data
SISPI carries output data from the MachXO2 Configuration Logic
to the slave SPI PROM
SPISO carries output data from the slave SPI PROM to the
MachXO2 Configuration Logic
MachXO2 Configuration Logic slave SPI chip select input. Pull
high externally whenever the MSPI port is active.
Clock used to time data transmission/reception from an external
SPI master device to the MachXO2 Configuration Logic.
SI carries output data from the external SPI master to the
MachXO2 Configuration Logic
SO carries output data from the MachXO2 Configuration Logic to
the external SPI master
MachXO2 Configuration Logic slave SPI chip select input. SN is
an active low input.
15
Description
Description