Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 33

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I C Port
The I2C_PORT allows you to preserve the I
There are two states to which the I2C_PORT preference can be set:
• ENABLE – This setting preserves the I
served and the EFB is instantiated with 'wb_clk_i' input connected to a valid clock source of at least 7.5x the
bus rate, an external I
you from over-assigning I/O to the port pins.
• DISABLE – This setting disconnects the I
purpose I/O.
In order to use the primary and secondary I
SDM Port
The SDM_PORT allows you to select the programming status pins after the MachXO2 device enters user mode.
There are four states to which the SDM_PORT preference can be set:
• DISABLE – This setting causes the PROGRAMN, DONE, and INITN status pins to become general purpose I/O.
• PROGRAM – This setting preserves the PROGRAMN pin when the MachXO2 device is in user mode. Asserting
this pin active low causes the MachXO2 device to reconfigure. The DONE and INITN pins are general purpose
I/O.
• PROGRAM_DONE – This setting preserves the PROGRAMN and DONE pins when the MachXO2 device enters
user mode. INITN is a general purpose I/O.
• PROGRAM_DONE_INITN – This setting preservers PROGRAM, DONE, and INITN in user mode.
Lattice recommends setting the SDM_PORT to PROGRAMN when using Master SPI or Dual Boot configuration
modes. The PROGRAMN pin is the only way to perform a "warm" reconfiguration of the MachXO2 device, unless
another configuration port is available to transmit a REFRESH command.
MCCLK Frequency
The MCLK_FREQ preference allows you to alter the MCLK frequency used to retrieve data from an external SPI
Flash when using EXTERNAL or Dual Boot configuration modes. The MachXO2 uses a nominal 2.08MHz (+/-
5.5%) clock frequency to begin retrieving data from the external SPI Flash. The MCLK_FREQ value is stored in the
incoming configuration data. It is not stored in the Feature Row. The MachXO2 device reads a series of padding
bits, a "start of data" word (0xBDB3) and a control register value. The control register contains the new
MCLK_FREQ value. The MachXO2 switches to the new clock frequency shortly after receiving the MCLK_FREQ
value. The MCLK_FREQ has a range of possible frequencies available from 2.08 MHz up to 133 MHz (see
Table 11). Take care not to exceed the maximum clock rate of your SPI Flash, or of your printed circuit board.
Lattice recommends having a back-up configuration port available in the event you specify a clock frequency that is
out of specification.
ENABLE_TRANSFR
The TransFR function used by the MachXO2 requires the configuration data loaded into the configuration SRAM,
and any future configuration data file loaded into the internal Flash memory have the ENABLE_TRANSFR set to
the ENABLE state. See the
figuration Using TransFR Technology
MachXO2 Programming and Configuration Usage Guide
2
C configuration port after the MachXO2 device enters user mode.
2
C port I/O when the MachXO2 is in user mode. When the pins are pre-
2
C Master controller can interact with the configuration logic. The preference also prevents
2
C port pins from the configuration logic. The port pins become general
2
C controllers in the EFB, the I2C_PORT must be in the ENABLE state.
TransFR Operation
for more information about using TransFR with the MachXO2.
section, and TN1087 Minimizing System Interruption During Con-
33
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I C