Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 16

and provides a reference clock for a SPI Flash attached to the MachXO2's Master SPI Configuration port. MCLK
actively drives until all of the configuration data has been received. When the MachXO2 enters user mode the
MCLK output tri-states. This allows the MCLK to become a general purpose I/O. The MCLK is reserved for use, in
most post-configuration applications, as the reference clock for performing memory transactions with the external
SPI PROM.
The MachXO2 generates MCLK from an internal oscillator. The initial frequency of the MCLK is nominally 2.08
MHz. The MCLK frequency can be altered using the MCCLK_FREQ parameter. You can select the MCCLK_FREQ
using the Diamond Spreadsheet View. For a complete list of the supported MCLK frequencies, see Table 11.
Table 11. MachXO2 MCLK Valid Frequencies (MHz)
During the initial stages of device configuration the frequency value specified using MCCLK_FREQ is loaded into
the FPGA. Once the MachXO2 accepts the new MCLK_FREQ value the MCLK output begins driving the selected
frequency. Make certain when selecting the MCLK_FREQ that you do not exceed the frequency specification of
your configuration memory, or of your PCB. Review the MachXO2 AC specifications in DS1035,
Data Sheet when making MCLK_FREQ decisions.
SN: The SN pin is the Slave SPI ports chip select. An external SPI bus master asserts the SN pin active low in
order to perform actions using the MachXO2's programming and configuration logic. The SN pin is available when
the MachXO2 is in the Feature Row HW Default Mode state, and in user mode when the Slave SPI port is set to the
ENABLE setting. The SN pin is a general purpose I/O in user mode when the Slave SPI port is set to the DISABLE
setting.
Proper operation of the MachXO2 depends upon maintaining the SN pin in the correct state:
• SN must be deasserted (that is, held High) when configuring using Master SPI mode. SN signal needs to be
clean during power up. Noise on SN pins may cause device failing to download from flash. SN must be asserted
when configuring using Slave SPI mode.
• SN must be deasserted when the MachXO2 is in user mode, and SPI memory transactions are initiated using
the internal WISHBONE bus
• SN must be deasserted when accessing the Configuration Logic in the MachXO2 using I
• When SN is asserted, CSSPIN must be deasserted. Deasserting CSSPIN places the shared SPI pins into a high
impedance state.
— The Master SPI port and the Slave SPI port share three common pins, SI/SISPI, SO/SPISO, and
MCLK/CCLK. The MachXO2 permits both ports to be available at the same time. They are not permitted to
be accessed at the same time. The Slave SPI and the Master SPI port must be time multiplexed when both
ports are enabled.
• SN must be deasserted, even if recovered for GPIO, whenever the Feature Row is Erased via
(e.g. embedded reconfiguration). If asserted, configuration may not complete successfully.
Lattice recommends the SN pin be pulled high externally to augment the weak internal pull-up.
CSSPIN: The CSSPIN pin is an active low chip select used by the Master SPI configuration mode to enable an
external SPI Flash. When the MachXO2 is programmed to configure in either External or Dual Boot mode the
MachXO2 Programming and Configuration Usage Guide
2.08 9.17
2.46 10.23
3.17 13.30
4.29 14.78
5.54 20.46
7.00 26.60
8.31 29.56
16
33.25
38.00
44.33
53.20
66.50
88.67
133.00
MachXO2 Family
2
C
2
sysConfig port
I C