Power-Up Sequence - Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual

Power-up Sequence

In order for the MachXO2 to operate, power must be applied to the device. During a short period of time, as the
voltages applied to the system rise, the FPGA will have an indeterminate state.
As power continues to ramp, a Power On Reset (POR) circuit inside the FPGA becomes active. The POR circuit,
once active, makes sure the external I/O pins are in a high-impedance state. It also monitors the V
input rails. The POR circuit waits for the following conditions:
• V > 1.06 V (or 2.1 V for HC devices)
CC
• V > 1.06 V
CCIO0
When these conditions are met the POR circuit releases an internal reset strobe, allowing the device to begin its
initialization process. The MachXO2 asserts INITN active low, and drives DONE low. When INITN and DONE are
asserted low the device moves to the initialization state, as shown in Figure 1.
Figure 2. Configuration from Power-On-Reset Timing
Initialization
The MachXO2 enters the memory initialization phase immediately after the Power On Reset circuit drives the
INITN and DONE status pins low. The purpose of the initialization state is to clear all of the SRAM memory inside
the FPGA.
The FPGA remains in the initialization state until all of the following conditions are met:
• The t time period has elapsed
INITL
• The PROGRAMN pin is deasserted
• The INITN pin is no longer asserted low by an external master
The dedicated INITN pin provides two functions during the initialization phase. The first is to indicate the FPGA is
currently clearing its configuration SRAM. The second is to act as an input preventing the transition from the initial-
ization state to the configuration state.
During the t time period the FPGA is clearing the configuration SRAM. When the MachXO2 is part of a chain
INITL
of devices each device will have different t
prevent other devices in the chain from starting to configure. Premature release of the INITN in a multi-device chain
may cause configuration of one or more chained devices to fail to configure intermittently.
The active-low, open-drain initialization signal INITN must be pulled high by an external resistor when initialization
is complete. To synchronize the configuration of multiple FPGAs, one or more INITN pins should be wire-ANDed. If
one or more FPGAs or an external device holds INITN low, the FPGA remains in the initialization state.
MachXO2 Programming and Configuration Usage Guide
V /V
CC CCIO
INITN
DONE
initialization times. The FPGA with the slowest t
INTIL
t
INITL
4
and V
CC CCIO0
parameter can
INTIL