Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 14

• The last function provided by INITn is to signal an error during the time configuration data is being read. Once
t has elapsed and the INITn pin has gone high, any subsequent INITn assertion signals the MachXO2 has
INTIL
detected an error during configuration.
The following conditions will cause INITN to become active, indicating the Initialization state is active:
• Power has just been applied
• PROGRAMN falling edge occurred
• The IEEE 1532 REFRESH command has been sent using a slave configuration port (JTAG, SSPI, I
BONE).
If the INITN pin is asserted due to an error condition, the error can be cleared by correcting the configuration bit-
stream and forcing the FPGA into the Initialization state.
Figure 7. Configuration Error Notification
PROGRAMN
The INITN pin of a MachXO2 device is not visible external to the device when in the Feature Row HW Default Mode
state. The INITN pin, when in this mode, is pulled high by default. The INITN behavior described in Figure 7 is only
visible outside the MachXO2 when the INITN pin is enabled.
The INITN can be recovered as a general purpose I/O. By default, the INITN pin is disabled. You can use the Dia-
mond Spreadsheet View to enable it.
If an error is detected when reading the bitstream, INITN will go low, the internal DONE bit will not be set, the
DONE pin will stay low, and the device will not wake up. The device will fail configuration when the following hap-
pens:
• The bitstream CRC error is detected
• The invalid command error detected
• A time out error is encountered when loading from the on-chip Flash
• The program done command is not received when the end of on-chip SRAM configuration or on-chip Flash
memory is reached
DONE: The DONE pin is a bi-directional open drain with a weak pull-up that signals the FPGA is in User mode.
DONE is first able to indicate entry into User mode only after an internal DONE bit is asserted. The internal DONE
bit defines the beginning of the FPGA Wake-Up state.
The DONE output pin is controlled by the SDM_PORT configuration parameter that is modified in the Diamond
Spreadsheet View. By default the DONE pin is a general purpose I/O when the MachXO2 is in the Feature Row
HW Default Mode state. The default mode causes the MachXO2 to automatically sequence through the Wake-Up
sequence after the internal DONE bit is asserted. The FPGA does not stall waking up waiting for the DONE pin to
be asserted high.
The FPGA can be held from entering User mode indefinitely by having an external agent keep the DONE pin
asserted low. In order to use DONE to stall entering User mode the SDM_PORT must enable the DONE I/O, and
the FPGA Feature Row must be programmed. (This feature is supported in Diamond 3.5 and later. Earlier versions
MachXO2 Programming and Configuration Usage Guide
t
INITL
INITN
DONE
Configuration
Error
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2
C or WISH-
Configuration
Started