Sysconfig™ Ports; Sysconfig Pins - Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual

Configuration Modes
The MachXO2 configuration SRAM memory must be loaded with valid configuration data before the FPGA will
operate. The MachXO2 provides only four methods of getting the configuration data into the SRAM memory. Each
of these methods has its own set of advantages. The four methods available are shown in Table 5.
Table 5. Configuration Modes
1149.1 JTAG
Self-Download Mode
External Download
Dual Boot Download
The primary configuration mode, for a majority of MachXO2 designs, is Self-Download Mode. It has an advantage
in configuration speed because the internal configuration clock runs at frequencies higher than can be applied to
an external memory. It does not require an extra PROM, which increases the cost of your product. It does not rely
on an external programmer to load the SRAM using the JTAG port.
The External Download mode's advantage is that it makes all of the User Flash Memory available for your use. You
do not have to be concerned about the Configuration Flash image overflowing into the UFM, or overflowing the
available internal Flash memory.
The Dual Boot mode's advantage is the MachXO2 configures more reliably. The MachXO2 loads the internal Flash
memory image first, and should that fail, a fail-safe configuration data image can be downloaded into the
MachXO2's SRAM, allowing the FPGA to continue to operate. A failed reprogramming of the internal memory, usu-
ally as a result of a loss of power, is the primary reason MachXO2 would fail to configure.
The JTAG port's advantage is that it provides the widest set of functions and features for programming, configuring,
and testing the MachXO2 system.
sysCONFIG™ Ports
Table 6. MachXO2 Programming and Configuration Ports
Interface
JTAG
sysCONFIG
Internal

sysCONFIG Pins

The MachXO2 provides a set of sysCONFIG I/O pins that you use to program and configure the FPGA. The sys-
CONFIG pins are grouped together to create ports (i.e. JTAG, SSPI, I
FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins in a config-
uration port group may be active, and used for programming the FPGA, or they can be reconfigured to act as gen-
eral purpose I/O.
Recovering the configuration port pins for use as general purpose I/O requires you to adhere to the following guide-
lines:
• You must DISABLE the unused port. You can accomplish this by using the Diamond Spreadsheet View's Global
Preferences tab. Each configuration port is listed in the sysCONFIG options tree.
MachXO2 Programming and Configuration Usage Guide
Mode
Port
JTAG (IEEE 1149.1 and IEEE 1532 compliant)
SSPI
MSPI
2
I C
WISHBONE
Number of Pins
4 (5)
0
4
0/4
4-wire or 5-wire JTAG Interface
Slave Serial Peripheral Interface (SPI)
Master Serial Peripheral Interface (SPI)
Inter-integrated Circuit (I
Internal WISHBONE bus interface
2
C, MSPI) that are used to interact with the
11
Max. Frequency
25 MHz
N/A
50 MHz
N/A / 50 MHz
Description
2
C) Interface