Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 17

CSSPIN pin is asserted to the attached SPI Flash. The MachXO2 asserts CSSPIN until all configuration data bytes
have been loaded, at which time the CSSPIN enters a high impedance state.
When the MachXO2 is in the Feature Row HW Default Mode state the CSSPIN is a general purpose I/O with a
weak pulldown. It must have an external pullup resistor when the External and Dual Boot configuration modes are
used. CSSPIN must ramp in tandem with the SPI PROM VCC input. It remains a general purpose I/O when the
FPGA enters user mode. You must ENABLE the Master SPI port to reserve CSSPIN for use by the internal SPI
Master logic.
When configuring from an external SPI Flash, ensure that the SPI Flash V
same level. Ensure that the SPI Flash V
Some SPI PROM manufacturers require the chip select input of the PROM ramp in unison to the PROMs VCC rail.
The CSSPIN pin, by default, has a weak pull-down resistor internally. Adding a 4.7 kOhm to 10 kOhm pull-up resis-
tor to the CSSPIN pin on the MachXO2 is recommended.
SI/SISPI: The SI/SISPI is a dual function bi-directional pin. The direction depends upon whether a Master or Slave
mode is active. The SI/SISPI is an input data pin when using the Slave SPI mode and is an output data pin when
using the Master SPI mode. In Master SPI mode, the MachXO2 drives SI/SISPI until all configuration data bytes
have been loaded, at which time the SI/SISPI enters a high impedance state.
At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE
in order to preserve this pin as SI/SISPI and allow access to the SPI interface.
SO/SPISO: The SO/SPISO pin is a dual function bi-directional pin. The direction depends upon whether a Master
or Slave mode is active. The SO/SPISO is an input data pin when using the Master SPI mode and is an output data
pin when using the Slave SPI mode.
At least one of the sysCONFIG preferences, SLAVE_SPI_PORT or MASTER_SPI_PORT, must be set to ENABLE
in order to preserve this pin as SO/SPISO and allow access to the SPI interface.
2
I C Configuration Port Pins
SCL: The MachXO2 provides an I
and time transactions on the I
2
I C controller is mastering transactions on the bus, and is an input when an external I
resources inside the MachXO2. SCL requires an external pull-up resistor in order to operate.
The SCL pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the
I2C_PORT and instantiate the Embedded Function Block (EFB) for the I
mode (see the I2C Configuration Mode
not ENABLE the I2C_PORT.
SDA: The SDA pin is the I
pull-up resistor in order to operate. The pin changes direction dynamically during data transactions on the I
The current state depends on the current bus master and the operation being performed by that master.
The SDA pin is available when the MachXO2 is in the Feature Row HW Default Mode state. You must ENABLE the
I2C_PORT and instantiate the EFB if you want the I
Configuration Mode section for details.) The SDA pin becomes a general purpose I/O if you do not ENABLE the
I2C_PORT.
JTAG Configuration Port Pins
The JTAG pins provide a standard IEEE 1149.1 Test Access Port (TAP). The JTAG port is the only configuration
port on the MachXO2 that is capable of performing configuration, programming, and multi-device configuration
functions. Programming and configuration over the JTAG port uses IEEE 1532 compliant commands. In addition to
the IEEE 1532 capabilities, the MachXO2 provides all of the mandatory IEEE 1149.1 Test Access Port commands
allowing printed circuit board assembly verification.
MachXO2 Programming and Configuration Usage Guide
meets is at the recommended operating level.
CC
2
C configuration port. The SCL is the I
2
C bus. It is a bi-directional, open-drain signal that is an output when the MachXO2
section for details.) The SCL pin becomes a general purpose I/O if you do
2
C serial data input/output pin. It is bi-directional, open-drain, and requires an external
CC
2
C Serial Clock pin, and is used to initiate
2
C port to continue to be available in user
2
C port to continue to be available in user mode (see the
17
and the MachXO2 V
CCIO2
2
C master is accessing
are at the
2
C bus.
I2C