Configuration Process And Flow - Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual

Configuration Process and Flow

Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration
and wake-up.
Figure 1. Configuration Flow
The MachXO2 sysCONFIG ports provide industry standard communication protocols for programming and config-
uring the FPGA. Each of the protocols shown in Table 1 provides a way to access the MachXO2 device's internal
Flash memory, or to load its configuration SRAM. The Memory Space Accessibility section provides information
about the capabilities of each sysCONFIG port.
The sysCONFIG ports capable of accessing the Flash memory have a priority order. Table 1 lists each of the sys-
CONFIG ports in their priority order. The MSPI configuration port does not have the ability to alter the Flash mem-
ory space, and as a result is not a factor in the sysCONFIG port priority scheme. The priority scheme is important
to be aware of, as a Configuration Logic operation using a low priority sysCONFIG port can be interrupted by a
higher priority sysCONFIG port. The operation of the Configuration Logic is not defined when a low priority sys-
CONFIG port is interrupted by a higher priority sysCONFIG port. Do not permit simultaneous access to the Config-
uration Logic using a sysCONFIG port.
MachXO2 Programming and Configuration Usage Guide
Power Up
VCC > 1.06V or
VCC > 2.1V (HC devices)
VCCIO > 1.06V
INITN and DONE
Driven Low
Initialization
INITN Released
Device refresh:
• PROGRAMN falling edge
• IEEE 1532 REFRESH command
Configuration
Device refresh
Write SRAM Memory
Device refresh
Wake Up
DONE Released
Device refresh
User Mode
Power not stable
PROGRAMN or
INITN=Low
PROGRAMN de-asserted and t expired
INITL
ERROR
INITN=Low
All configuration data received
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