User Mode; Clearing The Configuration Memory And Re-Initialization; Memory Space Accessibility - Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual

User Mode

The MachXO2 enters User Mode immediately following the Wake-Up sequence has completed. User Mode is the
point in time when the MachXO2 begins performing the logic operations you designed. The MachXO2 remains in
this state until one of three events occurs:
• The PROGRAMN input pin is asserted
• A REFRESH command is received via one of the configuration ports
• Power is cycled

Clearing the Configuration Memory and Re-initialization

The current user mode configuration of the MachXO2 remains in operation until it is actively cleared, or power is
lost. Several methods are available to clear the internal configuration memory of the MachXO2. The first is to
remove power and reapply power. Another method is to toggle the PROGRAMN pin. Lastly you can reinitialize the
memory through a Refresh command. Any active configuration port can be used to send a Refresh command.
• Assertion of the PROGRAMn input
• Cycling power to the MachXO2
• Sending the Refresh command using a configuration port
Invoking one of these methods causes the MachXO2 to drive INITN and DONE low. The MachXO2 enters the ini-
tialization state as described earlier.

Memory Space Accessibility

The two internal memories, Flash and SRAM, of the MachXO2 have the ability to be read and written. Each port on
the MachXO2 has a different level of access to each memory space. Table 2 provides a cross-reference of the
MachXO2 ports and the memory space they can access.
As can be seen from Table 1, the JTAG port has the ability to read and write both of the internal memory spaces.
No other port has ability to read the SRAM configuration memory. The JTAG port has the ability to access the two
memory spaces in either Offline or Transparent mode. Every other port has some limitation on the functions that
can be performed.
Table 1. Memory Space Accessibility of Different Ports
MachXO2 Programming and Configuration Usage Guide
Port
JTAG
SPI Port
2
I C Port
Internal WISHBONE
1. In Transparent mode only.
2. See the Clearing the Configuration Memory and Re-initialization
On-Chip Flash
Read Write Read
Yes Yes Yes
Yes Yes No
Yes Yes No
1 1
Yes Yes No
6
SRAM
Write
Yes
2
Refresh
2
Refresh
No
section.