Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual page 21

To ensure that the MachXO2 operates correctly using the MSPI configuration mode, make sure that:
• The POR of the SPI Flash device is lower than the POR of the MachXO2 or the SPI Flash must be powered first.
• SPI Flash Fmax is greater than the MachXO2 MCLK Fmax
• Board routing requirements to ensure the MachXO2 setup and hold time parameters are met. 
Refer to MachXO2 Family Data Sheet for detailed setup and hold time information.
Table 13. Master SPI Port Pins
Pin Name
MCLK
SISPI
SPISO
CSSPIN
Table 2 provides information about the amount of memory needed for MachXO2 configuration data by device den-
sity. Select a SPI Flash that accepts 03 hex Read Opcodes. The MachXO2 is only able to use the 03 hex Read
Opcode.
Figure 10. Master SPI Configuration Mode
The MachXO2 begins retrieving configuration data from the SPI Flash when power is applied, a REFRESH com-
mand is received, or the PROGRAMN pin is asserted and released. The MCLK/CCLK I/O takes on the Master
Clock (MCLK) function, and begins driving a nominal 2.08 MHz clock to the SPI Flash's SCLK input. CSSPIN is
asserted low, commands are transmitted to the PROM over the SI/SISPI output, and data is read from the PROM
on the SO/SPISO input pin. When all of the configuration data is retrieved from the PROM the CSSPIN pin is deas-
serted, and the MSPI output pins are tri-stated.
MachXO2 Programming and Configuration Usage Guide
Clock output from the MachXO2 Configuration Logic and Master SPI controller. Connect
MCLK to the SCLK input of the Slave SPI device.
Serial Data output from the MachXO2 to the slave SPI SI input.
Serial Data input to the MachXO2 configuration logic from the slave SPI SO output.
Chip select output from the MachXO2 configuration logic to the slave SPI Flash holding
configuration data for the MachXO2.
SPI PROM
C
Q
D
/CS
Function
MachXO2
4
JTAG
MCLK
SPISO
SISPI
CSSPIN
SPI
Controller
WISHBONE
21
Flash Memory
Configuration
Logic
MachXO2
Logic